Siddharth Patil

Siddharth was born in Ichalkaranji, India in 2000. He is currently pursuing a Master’s degree in Electrical Engineering at TU Delft, with a focus on Digital Design in Microelectronics. He completed his Bachelor’s degree in Electronics and Instrumentation from Manipal Institute of Technology in 2022. Following graduation, he worked as an Electrical Engineer at Cisco from 2022 to 2024. He will be starting his thesis project on Logic Gate and Lookup Table Networks as Low Power AI Models on FPGA with Imec in August 2025.

Program: MSc Microelectronics